This invention generally relates to a semiconductor memory device and, more particularly, relates to a structure and method of arranging and wiring memory blocks and external pads that can realize a fast flow of data.
FIGS. 29A and 29B of the accompanying drawings show a background dynamic type RAM. FIG. 29A is an external plan view whereas FIG. 29B is a plan view showing an inside of a package.
As shown in FIG. 29A, a dynamic type RAM (hereinafter referred to as a DRAM) type chip 100 is rectangularly parallelepipedic with short and long edges having a ratio of about 1:2. A group of pads 102 operate as input/output terminals of the chip 100. Two pad group arrangements are currently popular. The pad group 102 may be arranged either along an edge of the chip 100 or longitudinally along a central line of the short edges, the latter being referred to as a center pad arrangement.
As shown in FIG. 29B, with a chip 100 having a center pad arrangement, the pad group 102 of the chip 100 and the lead group of a package 200 are connected to each other by a bonding wire 300 when the chip 100 is housed in a resin-sealed package 200. Then, the DRAM can be provided with external input/output terminals on lateral sides of the package 200 along the longitudinal direction thereof.
Currently, efforts are being made to provide improved or newly developed DRAMs having a large memory capacity and enhanced functional features.
Enhanced functional features may be expressed in terms of bits. Multi-bit products include 4-bit, 8-bit, 16-bit and 32-bit DRAMs. The number of data input/output pads dramatically increases for multi-bit DRAMs of a higher order. This means that, with the center pad arrangement illustrated in FIGS. 29A and 29B, a chip 100 may not be able to accommodate a large number of pads.
Additionally, as a memory capacity is increased for DRAMs, more and more fine and minute circuit elements including memory cells and transistors are used. However, the efforts for producing fine and minute circuit elements can not necessarily catch up to the increased degree of integration of a DRAM, particularly in terms of a number of circuit elements so that a large chip 100 is inevitably used for each product. A large chip 100 means long wires used in a data transfer circuit to connect I/O pads and memory cells for storing data of a DRAM, and long control signal lines extending from a control circuit for controlling the data transfer circuit to the data transfer circuit itself. Long control signal lines and long wires used in the data transfer circuit by turn give rise to a problem of requiring a large space for accommodating the wires and a problem of a slow transmission rate for control signals and data signals.
FIG. 30 is a plan view of a background DRAM showing an arrangement of data lines.
As shown in FIG. 30, data lines include bit lines (BL) formed in memory cell arrays 104, DQ lines (DQ) arranged perpendicularly relative to the respective bit lines in sense amplifier regions 106 and connected to the bit lines by way of respective column gates (not shown), RWD lines (RWD) formed in bus regions 108 along center lines of 16 M core blocks in parallel with the bit lines BL and connected to the DQ lines by way of respective DQ buffers (not shown) and RD/WD lines (RD/WD) formed in peripheral region 110 and connecting the RWD lines and I/O buffers formed in the peripheral region 110.
Currently, the peripheral region 110 is produced by separating four 16 M core blocks from one another and the peripheral region 110 has a cross-like plan view. A control circuit (CNT.), internal power supply generating circuits (VPP, VREF, SSB), an address buffer and an I/O buffer are arranged within the cross-shaped peripheral region 110. More specifically, referring to FIG. 30, the control circuit is arranged at the crossing and the internal power supply generating circuits are arranged in the upper and lower regions of the shorter bar-like section of the peripheral region 110 separating the 16 M core blocks, while the address buffer and the I/O buffer are arranged respectively in the right and left regions of the longer bar-like section of the peripheral region 110 separating the 16 M core blocks.
Note that R/D stands for a row decoder and C/D stands for a column decoder in FIGS. 29A and 30.
With the data line arrangement of FIG. 30, the longest data line connecting a memory cell and the I/O buffer is about as long as the longer edge of the chip 100.
In the field of semiconductor memory devices including DRAMs, multi-bit devices are inevitably accompanied with a large chip size. Multi-bit devices of a higher order involve a large number of pads and a large chip size involves long control signal lines and long data lines. While these problems may be currently negligible, they will become serious in the future with the trend of seeking multi-bit devices of an even higher order. For instance, a large number of pads will pose a problem of the difficulty with which they are appropriately arranged. Long control signals lines and data lines will make it difficult to maintain the throughput of a semiconductor memory device to a desired level.